Introduction

Chip design IDE in the browser. Write Verilog, run LibreLane on our servers, read back timing and power and a GDS file. Nothing to install locally.

What is Vulkos#

A full chip layout means running synthesis, placement, routing, and signoff. That stack is usually LibreLane (OpenLane) plus the sky130 PDK, configured by hand and run on your own machine. Vulkos runs the same stack on cloud hardware and gives you the files and logs in a web editor.

  • LibreLane RTL-to-GDS on sky130, on managed runners
  • Run history, analysis, GDS viewer in the IDE
  • Starter projects ship with Verilog, a testbench, and a working config.json

How it works#

  1. Edit your .v files under src/. Editor
  2. Run the testbench under tb/ before you pay for a full build. Testbench
  3. Check config.json (design name, clock, file list), then press Run. Running LibreLane
  4. Read timing, power, DRC, and open the layout. Analysis

You will spend most of your time in steps 1 and 4. Step 3 is mostly waiting on the runner.

Who it's for#

Anyone who writes Verilog and does not want to maintain a local EDA setup: students, hobbyists, people taping out on sky130. If you are starting from scratch, the Learning courses cover the basics. For a first run through the IDE, use the Quickstart.

Next steps#

Next Quickstart: your first chip