Schematic viewer

The schematic viewer shows the gate-level netlist your RTL synthesised into — the logic as a network of gates, before it's placed on a die. It's the bridge between the Verilog you wrote and the layout you got.

The gate-level netlist#

After synthesis, your design exists as interconnected cells. The schematic draws that network so you can see what your code actually became — how an operator expanded into gates, or where your registers ended up.

The elaboration journey#

The same logic can be shown at two levels of detail:

• Generic gates — the logic expressed as abstract gates, closest to how you think about the design.
• Technology cells — the same logic mapped onto concrete sky130 standard cells, which is what gets placed and routed.

Moving between the two shows the elaboration journey: how an abstract design becomes a specific set of physical cells.

Using it to debug#