Quickstart: your first chip

This guide takes you from an empty project to a manufacturable GDS layout. It uses a small 4-bit counter, but the steps are identical for any design.

Before you start#

You need a Vulkos account and a project open in the IDE. From the dashboard, click New project or open the example project created for you on sign-up. Everything below happens inside the IDE workspace.

Build your first chip#

1. 1

   Open your design file

   In the file explorer on the left, open src/counter.v. This is your Verilog source. The example design is a synchronous 4-bit up-counter:

   module counter (
       input  wire       clk,
       input  wire       rst,
       output reg  [3:0] count
   );
       always @(posedge clk) begin
           if (rst) count <= 4'b0000;
           else     count <= count + 1;
       end
   endmodule

2. 2

   Check the testbench

   Open the file under tb/. The testbench drives inputs and checks outputs so you can confirm the design is correct before running the full flow. See The testbench for details.
3. 3

   Review the LibreLane config

   Open config.json in the file explorer. Template projects include a working config. Check that DESIGN_NAME matches your top module, VERILOG_FILES lists your source, and CLOCK_PORT and CLOCK_PERIOD match your clock. Edit in the JSON view or switch to the guided form. See The LibreLane config for a field-by-field walkthrough.
4. 4

   Run the flow

   Click Run in the top bar. Vulkos provisions a cloud runner and starts the RTL-to-GDS flow: synthesis, floorplan, placement, clock-tree synthesis, routing, and signoff. The pipeline status shows each stage as it completes, and live logs stream into the terminal panel.
5. 5

   Open the results

   When the run finishes, open the Analysis tab for timing, power, and area, and the GDS viewer to see the physical layout of your chip. That layout is the file a foundry would manufacture from.

What just happened#

Behind that single Run click, a full open-source physical-design flow executed on cloud compute. The next sections break down each part: the IDE, the configuration, the pipeline, and analysis.