FAQ
Answers to the questions new users ask most.
Do I need to install anything?
No. Vulkos runs entirely in your browser. The editor and the full RTL-to-GDS flow run on our cloud infrastructure.
What hardware description language do you support?
Verilog. You write standard synthesizable Verilog RTL and a self-checking testbench, and the flow takes it from there.
What does "RTL-to-GDS" mean?
RTL (your Verilog) is the logical description of your design. GDS is the physical layout file a foundry manufactures from. Synthesis, placement, routing, and signoff turn one into the other.
Which technology does it target?
Vulkos runs the open-source LibreLane (OpenLane) flow against the SkyWater sky130 open PDK by default. Template projects include a working config for this PDK.
Do I need to know the toolchain to use it?
You need to know Verilog and how to read a config file, but you do not need local EDA tools installed. Template projects ship with working configs you can adjust in the editor or guided form.
How long are my runs kept?
Runs and their artifacts are retained according to your plan. See Storage & retention for the specifics and the per-plan limits.
What happens when I hit my weekly limit?
Compute minutes reset weekly. If you regularly run out, upgrading to Pro raises the ceiling. See Plans & usage.
Is my design private?
Yes. Your projects, files, and runs are scoped to your account and are not visible to other users.
I'm new to chip design. Where should I start?
The Learning courses take you from logic fundamentals to a finished layout, and the Quickstart builds your first chip in about ten minutes.