Power

Power analysis estimates how much your chip will draw once it's running. It's an estimate from the post-layout netlist, not a measurement, but it's a reliable way to compare designs and spot the hungry parts.

Dynamic vs leakage#

• Dynamic power is burned when signals switch — it scales with clock frequency and how much of the design is active. This usually dominates.
• Leakage power is drawn continuously just from transistors being powered, even when nothing toggles. It grows with cell count and area.

Reading the breakdown#

The report attributes power across the design — by net and by cell type — so you can see whether the clock network, the registers, or a particular block accounts for most of it. The clock tree is often a surprisingly large share, because it switches every cycle across the whole die.

Lowering power#

• Slow the clockif you don't need the speed — dynamic power scales directly with frequency.
• Shrink the design — fewer cells means less leakage and a smaller clock tree. See Synthesis & area.