Signoff
Signoff is the final verdict on whether your layout could actually be manufactured. Two checks matter most: DRC and LVS. A run that passes both has produced a clean, fabricable GDS.
What signoff checks#
Earlier stages build the layout; signoff proves it's correct. It confirms the physical geometry obeys the foundry's rules and that the layout still matches the circuit you designed. These run automatically at the end of every flow.
DRC — design-rule checks#
DRC verifies the layout against the manufacturing rules of the sky130 process: minimum spacing, wire widths, layer overlaps, and so on. A DRC violation means a shape on the die breaks a rule the foundry guarantees, so the design isn't yet manufacturable.
- A clean DRC result means zero rule violations.
- Violations point at a location and a rule — usually a routing or spacing issue the flow couldn't resolve, often tied to congestion.
LVS — layout versus schematic#
LVS confirms the physical layout implements the same netlist as your synthesised design — that placement and routing didn't accidentally connect, drop, or short anything. Passing LVS means what got built matches what you described.
When signoff fails#
A signoff failure usually traces back to congestion
Most DRC failures come from a design that's packed too tightly to route cleanly. Lowering utilisation gives the router room to obey the rules — see Synthesis & area. If errors persist, ask the assistant to read the signoff report; it can usually localise the problem. See Troubleshooting failures.