Running LibreLane
Click Run in the top bar to start an RTL-to-GDS build. Vulkos provisions a cloud runner, sends your project and config, and streams progress back to the IDE.
Starting a run#
Before you run, confirm three things:
- Your RTL compiles cleanly and the testbench passes.
config.jsonnames the correct top module and lists the right Verilog files.- You have compute minutes remaining this week (shown in your account usage panel).
Press Run. The pipeline status control in the top bar shows the active stage.
While it runs#
Live logs stream into the terminal panel at the bottom of the IDE. Stages such as synthesis, floorplan, placement, clock-tree synthesis, routing, and signoff appear in order. Small designs often finish in a few minutes; larger ones take longer.
You can keep editing files while a run is in progress, but changes will not affect the current run. Start a new run after saving to pick up edits.
When it finishes#
A successful run unlocks the analysis workspace (timing, power, area, signoff) and the GDS and schematic viewers. The run is saved to your project history so you can reopen it later.
When it fails#
If a stage fails, the terminal shows the error and Vulkos highlights the likely fix inline when possible. Common causes include config typos, timing violations, and DRC issues. See Troubleshooting failures for patterns and recovery steps.
Iterate quickly
Fix the reported issue, save, and run again. Most chip design work is a loop of small changes followed by another build.