Pipeline stages
A LibreLane run takes your Verilog and turns it into a manufacturable layout through a fixed sequence of stages. Each one hands its result to the next, and a failure stops the flow at the stage that hit the problem.
The stages in order#
- 1
Synthesis
Your RTL is mapped to real standard cells from the PDK library. The output is a gate-level netlist — the same logic, now expressed as physical gates. Cell count and area come from here. - 2
Floorplanning
The die outline is set, power rails are laid down, and I/O pins are placed. This decides how much room the rest of the flow has to work with. - 3
Placement
Every standard cell is given a position on the die, packed to keep connected cells close and the design routable. - 4
Clock-tree synthesis (CTS)
A balanced network is built to deliver the clock to every flip-flop with minimal skew, so the whole design switches together. - 5
Routing
The metal wires connecting all the cells are drawn across the available layers. This is often the longest stage on a congested design. - 6
Signoff
Final checks confirm the layout is correct and manufacturable: timing analysis, plus DRC (design-rule checks) and LVS (layout-versus-schematic). The result is your GDS.
Following along during a run#
As the flow runs, the terminal streams each stage's output live, so you can see where it currently is. When it finishes, the analysis workspace breaks the results down by the same stages — timing from signoff, area from synthesis, and so on.
Where failures show up
If a run fails, the stage name in the logs tells you where to look: a synthesis error points at your RTL or config, while a routing or timing failure usually means the design is too dense or the clock target is too aggressive. See Troubleshooting failures.