The testbench

A testbench is Verilog that exercises your design and checks the outputs. Vulkos expects a self-checking testbench in tb/ so you can verify logic before a costly physical run.

Why testbenches matter#

The RTL-to-GDS flow turns your design into a layout. If the logic is wrong, you still pay compute minutes for a build that does not match your intent. A passing testbench gives you confidence the behavior is correct first.

Self-checking pattern#

Template testbenches follow a common structure:

• Instantiate the design under test and generate a clock (and reset if needed).
• Drive stimulus: known inputs over time.
• Compare outputs against expected values and call $finish on mismatch.
• Print a clear PASS or ERROR message so logs are easy to read.

Open tb/counter_tb.v in the seeded counter project for a complete example with reset checks and increment verification.

Running verification#

Verification runs as part of the broader flow when configured, or you can simulate the testbench on its own depending on your project setup. A failure surfaces in the terminal with the assertion or mismatch that triggered it.