Timing
Timing analysis answers one question: does your design run at the clock speed you asked for? It's the result you'll check first after almost every run.
Setup, hold & slack#
Signoff timing reports two kinds of constraint. Setup checks that a signal arrives early enough before the next clock edge; holdchecks that it doesn't arrive too early and corrupt the current cycle.
- Slack is the margin on a path. Positive slack means the path meets its constraint with room to spare.
- Worst negative slack (WNS) is the single tightest failing path. If WNS is negative, the design does not close timing at the requested
CLOCK_PERIOD.
Hold violations are different
Setup failures usually mean “too slow” — relax the clock and they go away. Hold failures are about short paths and aren't fixed by slowing the clock; the flow inserts buffers to fix most of them automatically.The critical path#
The critical path is the slowest route through your logic — the chain of gates that sets the maximum frequency. The timing report traces it cell by cell so you can see exactly where the delay accumulates.
Critical path explorer
Interactive demo · coming soon
Closing timing#
- Relax the target. Increasing
CLOCK_PERIODis the quickest way to turn negative slack positive when the speed isn't critical. - Shorten the path. Pipeline a long combinational chain, or restructure the logic so fewer gates sit between registers.
For where timing sits in the overall flow, see Pipeline stages.