Simulation results
Simulation runs your design against its testbench to check it actually behaves correctly — the logic verification step, separate from the physical build. It's how you catch a functional bug before committing compute to a full run.
Pass / fail results#
A self-checking testbench drives inputs and asserts the expected outputs. The result is a clear pass or fail, plus any messages your testbench printed.
- Pass — the design produced the expected outputs for every case the testbench exercised.
- Fail— an assertion didn't hold. The message and the cycle it fired on tell you what diverged and when.
A pass is only as good as the testbench
Simulation proves your design matches the testbench, not that the testbench covers everything. Exercise the corner cases that matter to you. See The testbench.Waveforms#
When a test fails, waveforms are the fastest way to see why. They show every signal over time, so you can trace a wrong output back to the inputs and internal state that produced it.
Waveform viewer
Interactive demo · coming soon
Why simulate first#
A physical run takes minutes and only checks that your RTL can be built— not that it's correct. Simulation is fast and catches logic bugs early, so verifying here first saves you from spending a full run to discover a functional mistake. For the whole loop, see The Vulkos workflow.