Generating a LibreLane config
Writing a LibreLane config by hand means knowing which keys matter. Instead, let the assistant read your design and produce a complete, valid configuration you can use as a starting point.
Why generate a config#
A config that doesn't match your RTL is the most common reason early runs fail — wrong design name, a missing source, the wrong clock port. Generating it from your actual files sidesteps all three, because the assistant reads the design before it writes the settings.
How it works#
Ask the assistant to generate a config for your project. It will:
- Read your Verilog to find the top module and clock port.
- Fill in the essentials —
DESIGN_NAME,VERILOG_FILES,CLOCK_PORT,CLOCK_PERIOD— and a sensible sky130 PDK block. - Propose the result as a reviewable change.
Config generation
Interactive demo · coming soon
Review before applying#
A starting point, not the last word
The generated config is meant to be edited. Review the diff, apply it, then tune the values that matter for your design — clock period in particular. For what each field controls, see Key parameters, and for how edits are applied, see Agent edits.