Key parameters

Most designs only need a handful of settings to go from RTL to GDS. These are the fields you'll set on almost every project, and the ones worth understanding first.

Design & sources#

• DESIGN_NAME — your top-level module name. It must match the module in your Verilog exactly, or synthesis can't find an entry point.
• VERILOG_FILES — the synthesizable sources to build. List files individually or use the dir::src/ prefix to include every .v in a folder.

Clock & timing#

• CLOCK_PORT — the name of your clock input. LibreLane uses it to drive timing analysis and clock-tree synthesis.
• CLOCK_PERIOD — the target clock period in nanoseconds. It sets the timing goal the flow tries to meet: 10.0 targets 100 MHz, 5.0 targets 200 MHz.

A shorter period asks for a faster chip and is harder to close. If you see negative slack in the timing results, relaxing CLOCK_PERIOD is the first thing to try.

PDK & standard cells#

Template projects target the open-source sky130 process. Two settings select it:

{
  "PDK": "sky130A",
  "STD_CELL_LIBRARY": "sky130_fd_sc_hd"
}

sky130_fd_sc_hd is the high-density standard-cell library — a good default for most designs. You rarely need to change these unless you're deliberately targeting a different library.

Common tuning knobs#

Die size and density

The starter config sets FP_SIZING to absolute and fixes DIE_AREA to a Tiny Tapeout tile, so the die is a size you choose rather than one derived from utilisation. To give a design more room, move DIE_AREA up to the next tile size listed in the config. A 1x1 tile holds roughly 4,000 standard cells at the default density.

PL_TARGET_DENSITY_PCT sets how densely cells are packed into that die (as a percentage). Lower values give the router more room and can fix congestion.

Synthesis effort

Synthesis strategy options trade run time against area and timing. The defaults are a sound starting point — reach for these only once a design builds cleanly and you want to optimise.