The Vulkos workflow

Four stages, repeated until the numbers look right. The IDE panels map roughly to these.

Write#

Your design lives in Verilog under src/. The top module name must match DESIGN_NAME in the config. Clock and reset ports are what the flow uses for timing.

• Syntax highlighting, autosave, lint markers in the editor.
• Keep testbenches in tb/, RTL in src/.

Verify#

Run the testbench before a full LibreLane build. A self-checking bench drives inputs, compares outputs, and exits with PASS or ERROR. Functional bugs caught here cost seconds of sim time, not minutes of compute on the runner.

Run#

config.json tells LibreLane which files to build, the clock period, and the PDK. Template projects include a working config. Open it, fix anything that does not match your RTL, then hit Run. See The LibreLane config for the fields that usually need changing.

The runner goes through synthesis, floorplan, placement, CTS, routing, and signoff. Logs stream to the terminal. If a stage fails, fix the cause and run again.

Analyze#

A finished run gives you timing slack, power, area, DRC/LVS, plus GDS and a gate-level schematic. Check whether you met the clock target and whether the layout is clean. Change the RTL or tighten the clock, run again, compare against the last run in history.