Synthesis & area
Synthesis turns your RTL into real gates from the standard-cell library. The numbers it produces — how many cells, how much area — are the first sign of how big and complex your design really is.
What synthesis produces#
The synthesiser maps your Verilog onto concrete cells: adders become chains of gates, always blocks become flip-flops, and so on. The result is a gate-level netlist — the same behaviour, now expressed in hardware you can place and route. You can inspect it in the schematic viewer.
Cell count & area#
- Cell count is how many standard cells your design used. A jump in cell count after an RTL change is a quick signal that something grew unexpectedly.
- Area is the silicon those cells occupy. It drives die size, leakage power, and how hard the design is to route.
Watch for accidental bloat
Wide arithmetic, large multipliers, and big memories synthesise into a lot of cells. If area looks high, check whether an operator in your RTL is wider than it needs to be.Utilisation#
Utilisation is how densely the core is packed — the cell area as a fraction of the floorplan. Set the target with FP_CORE_UTIL: pack too tightly and routing congests; leave too much space and the die is needlessly large. If a run fails in routing, lowering utilisation is a common fix. See Key parameters.