The LibreLane config

config.json is the instruction sheet for LibreLane. It names your design, lists the Verilog sources, sets timing targets, and selects the process design kit (PDK).

What config.json does#

When you click Run, Vulkos sends your project files and this config to a cloud runner. LibreLane reads the JSON and executes synthesis through signoff using those settings. A mismatch between the config and your RTL (wrong module name, missing file, wrong clock port) is a common source of early failures.

Essential fields#

These fields appear in every sky130 template project:

{
  "DESIGN_NAME": "counter",
  "VERILOG_FILES": ["dir::src/counter.v"],
  "CLOCK_PORT": "clk",
  "CLOCK_PERIOD": 10.0,
  ...
}

• DESIGN_NAME must match your top-level module name exactly.
• VERILOG_FILES lists every synthesizable source. The dir:: prefix includes all .v files in that folder.
• CLOCK_PORT names the clock input LibreLane uses for timing closure.
• CLOCK_PERIOD is the target clock period in nanoseconds (10.0 means 100 MHz).

See Key parameters for the rest of the commonly tuned settings.

PDK block#

Nested under pdk::sky130A and scl::sky130_fd_sc_hd, you can override PDK-specific values such as the clock period for that library. Template projects target the SkyWater sky130 open PDK with the high-density standard-cell library.

Editing the config#

Open config.json in the IDE. Use raw JSON if you already know LibreLane, or switch to the guided form for the fields you touch most often. Both views stay in sync. See GUI form vs JSON.