Digital Design Fundamentals

• 01Combinational Logic & Delay
• 02Sum of Products
• 03Product of Sums
• 04The 2-to-1 MUX
• 05The 4-to-1 MUX
• 06Hierarchy
• 07Adding & Subtracting in Binary
• 08Half Adders
• 09Full Adders
• 10Decoders & Traffic Control

What you'll learn

• Trace propagation delay and identify the critical path through logic
• Turn any truth table into gates with sum of products or product of sums, and simplify on a K-map
• Build multiplexers and compose them into wider selection trees using hierarchy

• 01Setting up a Verilog design
• 02Assign and Combinational Logic
• 03The 2-to-1 MUX in Verilog
• 04The 4-to-1 MUX in Verilog
• 05The Half Adder in Verilog
• 06The Full Adder in Verilog
• 07The 2-to-4 Decoder in Verilog

What you'll learn

• Write a Verilog module with correctly declared input and output ports
• Tell wire from reg and know when each applies
• Describe combinational logic with continuous assignment

• 01Clocks & Sequential Design
• 02Latches
• 03Flip-Flops
• 04Registers & Enabled Storage
• 05Shift Registers
• 06Counters
• 07Moore State Machines
• 08Mealy State Machines
• 09Designing an FSM: Traffic Light

What you'll learn

• Explain what a clock is and how it turns memoryless logic into stateful, sequential design
• Tell a level-sensitive latch from an edge-triggered flip-flop, and read setup and hold timing
• Build registers with write enables and choose between synchronous and asynchronous reset

• 01Clocked Blocks in Verilog
• 02Blocking vs Non-Blocking
• 03Coding Resets
• 04Counters and Shift Registers in Verilog
• 05FSMs in Verilog
• 06State Encoding
• 07Capstone, Traffic Light Controller

What you'll learn

• Describe clocked hardware with always @(posedge clk) and reg
• Use non-blocking assignments correctly and avoid simulation to synthesis mismatch
• Code synchronous and asynchronous resets

• 01What Verification Is
• 02The Cost of Bugs
• 03The Testbench Idea
• 04Building a Testbench Shell
• 05How a Simulation Runs
• 06Clocks and Resets in a Testbench
• 07Applying Stimulus
• 08Watching Signals with $display and $monitor
• 09Self-Checking Testbenches
• 10Writing a Self-Checking Testbench
• 11Reusable Checks with Tasks
• 12Testbench Best Practices
• 13Reading Waveforms
• 14Debugging from a Trace

What you'll learn

• Explain what verification is and why it dominates chip design effort
• Describe a testbench as a harness that drives and checks a design under test
• Build a testbench shell, generate a clock and reset, and apply stimulus

• 01Setup, Hold and Clock-to-Q
• 02Critical Paths and Slack
• 03Pipelining for Throughput
• 04Metastability and Synchronizers

What you'll learn

• Read the dynamic timing of a flip-flop: setup, hold and clock-to-Q
• Find a critical path and reason about maximum clock frequency and slack
• Explain how pipelining trades latency for throughput

• 01From RTL to Silicon
• 02ASIC versus FPGA
• 03Where to Go Next

What you'll learn

• Trace at a high level how RTL becomes physical hardware: synthesis, place and route, sign-off
• Compare ASIC and FPGA implementation and their trade-offs
• Know where to go next across the course family