Digital Design Fundamentals·Signals, Bits & Logic
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A processor constantly chooses between values: the result of an add or the result of a subtract, data from cache or data from memory. The circuit that chooses is the multiplexer, or MUX.
A 2-to-1 MUX has:
a and bsyThe rule: s = 0 routes a to the output. s = 1 routes b.
A processor constantly chooses between values: the result of an add or the result of a subtract, data from cache or data from memory. The circuit that chooses is the multiplexer, or MUX.
Figure: The trapezoid MUX symbol with data inputs a and b entering the left side, the select signal s entering from below
A 2-to-1 MUX has:
a and bsyThe rule: s = 0 routes a to the output. s = 1 routes b.
This is a live 2-to-1 MUX, built from the gates you already know: one NOT, two ANDs and one OR.
Try it:
s = 0 and toggle a. The lamp copies a.b. Nothing happens: b is cut off from the output.s = 1 and repeat. Now b drives the lamp and a is ignored.Because the MUX ignores one input at a time, its behaviour compresses into two rows:
| s | y |
|---|---|
| 0 | copies a |
| 1 | copies b |
Written out as a full truth table, the same fact looks like this:
| s | a | b | y |
|---|---|---|---|
| 0 | 0 | x | 0 |
| 0 | 1 | x | 1 |
| 1 | x | 0 | 0 |
| 1 | x | 1 | 1 |
The x means don't care: that input has no effect on that row. Don't-cares are everywhere in hardware design. They mark the inputs a circuit is free to ignore.
"Route a when s is 0, route b when s is 1" translates directly into logic:
Read each half:
Exactly one of the two AND terms is open at any moment. The OR gate merges whichever path is open onto the output.
Figure: Gate-level schematic of the 2-to-1 MUX: input s splits into a NOT gate, two 2-input AND gates receive a with not-s and b with s
The equation maps one-to-one onto hardware:
sa while s = 0b while s = 1Scroll back to the live circuit in step 2 and check it against this schematic. It is the same four gates.