The 2-to-1 MUX in Verilog

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The 2-to-1 MUX in one table

A quick reminder from Module 2. The 2-to-1 MUX routes one of two inputs to the output: s = 0 picks a, s = 1 picks b.

A trapezoid 2-to-1 MUX symbol with data inputs a and b on the left, output y on the right, and select line s entering from below

s	y
0	a
1	b

That table is a two-term sum of products: one product passes a while s is 0, the other passes b while s is 1.

y = (a \cdot \overline{s}) + (b \cdot s)

The 2-to-1 MUX in one table

A quick reminder from Module 2. The 2-to-1 MUX routes one of two inputs to the output: s = 0 picks a, s = 1 picks b.

Figure: A trapezoid 2-to-1 MUX symbol with data inputs a and b on the left, output y on the right, and select line s entering from below

s	y
0	a
1	b

That table is a two-term sum of products: one product passes a while s is 0, the other passes b while s is 1.

y = (a \cdot \overline{s}) + (b \cdot s)

Confirm it in the circuit

Toggle s and watch the output. s = 0 sends a through, s = 1 sends b, exactly the two rows of the table.

Write the equation

Turn the truth table into Verilog. In design.v, drive y with one continuous assignment that matches the table: a when s is 0, b when s is 1.

You can write the Boolean equation with &, | and ~, or use the conditional operator ? :. Both match the table. The testbench prints a live trace over every input combination and passes when it prints VULKOS_RESULT: PASS.