Assign and Combinational Logic

The assign statement

Continuous assignment wires an output to an expression. Whenever an input on the right changes, the output on the left updates. That is exactly what a combinational circuit does.

assign y = a & b;

This is not "set y once". It is a permanent connection: y is the AND of a and b, forever. It describes an AND gate, not an instruction.

Gates as symbols

Verilog has a symbol for each gate you know. These are bitwise operators, working bit by bit on their operands:

• AND is &, as in assign y = a & b;
• OR is the pipe symbol, as in assign y = a | b;
• NOT is ~, as in assign y = ~a;
• XOR is ^, as in assign y = a ^ b;

Combine them with parentheses to build any expression. Two ANDed signals ORed with an inverted third is assign y = (a & b) | ~c;.

What you will describe

Before writing code, poke the circuit. This is the AND, OR and NOT logic from Module 1.

Toggle a and b and watch the three outputs. In the exercise you will describe a circuit like this one in Verilog: a few gates, each one line of assign.

The habit is worth forming now. Understand the circuit, then write the code that produces it.

Build compound logic

Describe a circuit with three inputs a, b, c and one output y that computes:

Write a single continuous assignment in design.v using &, | and ~.

The testbench prints a live truth-table trace and checks all eight input combinations. It passes when it prints VULKOS_RESULT: PASS.