Digital Design Fundamentals·RTL for Combinational Logic

Assign and Combinational Logic

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The assign statement

Continuous assignment wires an output to an expression. Whenever an input on the right changes, the output on the left updates. That is exactly what a combinational circuit does.

Verilog

assign y = a & b;

This is not "set y once". It is a permanent connection: y is the AND of a and b, forever. It describes an AND gate, not an instruction.