The Half Adder in Verilog

The half adder in one table

A reminder from Module 2. The half adder adds two bits and produces a sum bit and a carry bit. Its truth table:

Read carry and sum together and they are the 2-bit total of a + b.

Confirm it in the circuit

Toggle a and b and check the table row by row: sum is high when the inputs differ, carry only when both are 1.

Two outputs, two assigns

A module drives each output with its own continuous assignment, so a two-output module needs two lines:

assign sum   = ...;
assign carry = ...;

Look at the table to fill each right-hand side. sum is 1 exactly when the two inputs differ. carry is 1 exactly when both inputs are 1. Each of those matches one gate you already know.

Build a half adder

Turn the truth table into Verilog. In design.v, write one continuous assignment for each output: sum is 1 when a and b differ, and carry is 1 when both are 1. Match each to a gate operator (^, &, ~).

The testbench prints a trace and checks all four input pairs. It passes when it prints VULKOS_RESULT: PASS.