Teach chip design without the lab setup.
Vulkos runs the open-source chip design flow in the browser. Your students write Verilog, simulate it and see a manufacturable layout in a single session, and you set the labs and follow the class from one place.
What happened when we ran it with Cambridge attendees.
- 33 of 43
- said yes to using Vulkos in their own course, lab or research group. Ten said maybe, none said no.
- 2.1 to 3.4
- average agreement (out of 5) with “I could design a simple digital chip myself”, before and after the session.
- 4.6 / 5
- average workshop rating, with 36 of 43 finishing without getting stuck.
From 43 responses to the survey after our workshop at the University of Cambridge on 21 October 2026. Attendees ranged from first years to PhD researchers and staff. At our Riga workshop on 16 October, 40 of 51 attendees said they would consider a career in chips.
How a lab runs on Vulkos
Set the lab, not the setup
Students open a link and start. The full open-source flow runs on our servers, so there are no virtual machines, containers or licences to arrange, and it works on whatever laptops they already have.
Verilog to layout in one session
Write RTL, simulate it against a testbench, then run synthesis, placement and routing and look at the finished layout, all in the same tab. A class can see the whole path in two hours.
Checked against your testbench
Hand out an assignment and students submit from the browser. Their design is checked against the testbench you provide, and you choose the order the labs appear in.
See how the class is doing
Every student has a progress view, so you can see who has finished, who is stuck and where before the next session, instead of finding out in the exam.
In their words
“As somebody that has taught lab courses, designing an introductory class lab using Vulkos could be very educational.”
“With Vulkos, I could start working on the problem without any of the tedious setup!”
“I am a Mac OS user so being able to use LibreLane without setting up a Virtual Machine or using Docker was great.”
Quoted with permission from attendees of our Cambridge workshop.
Fits the course you already teach
Alongside your course
Keep your syllabus and teaching order. We add interactive labs and demonstrations to the modules you already run, rather than asking you to rebuild them.
Ready-made fundamentals
Digital Design Fundamentals takes students from binary and gates through Verilog and state machines to the RTL-to-silicon flow, in 8 modules and 62 lessons. The first three modules are free to read without an account.
An assistant that explains
The built-in assistant reads the student’s own design, explains errors in place and suggests fixes, which takes the repeated questions off your teaching assistants.
Run a pilot with one class.
Tell us about the course, the cohort size and the term you are planning. We will help you set up a first lab, and cover pricing for departments on the Enterprise plan. Students can always start on the free plan.