Digital Design Fundamentals·Signals, Bits & Logic
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Schematics have their own vocabulary, and the rest of this course uses it freely. Start with the simplest element.
One net, one value. If two gates drove the same net they could disagree, so in ordinary logic every net has exactly one driver.
Schematics have their own vocabulary, and the rest of this course uses it freely. Start with the simplest element.
Figure: A small schematic where one gate output fans out to three gate inputs
One net, one value. If two gates drove the same net they could disagree, so in ordinary logic every net has exactly one driver.
A 32-bit number needs 32 wires. Drawing 32 lines would bury every schematic, so grouped wires get one thick line and a name: a bus.
Figure: A schematic comparison: eight separate thin wires drawn individually on the left
data[7:0] names an 8-bit bus: bit 7 is the MSB, bit 0 the LSBdata[3] picks out a single wire from the bundleTen terms cover most of what circuit designers say. Skim the table now, and come back whenever one resurfaces later in the course.
| Term | Meaning |
|---|---|
| High / low | Logic 1 / logic 0 |
| Asserted | Driven to its active state (usually 1) |
| Rising edge | The instant a signal steps from 0 to 1 |
| Falling edge | The instant a signal steps from 1 to 0 |
| Schematic | The drawing of gates and the nets between them |
| Netlist | The same circuit as a list: every gate and every connection |
| Combinational | Logic whose output depends only on its current inputs |
| Sequential | Logic that remembers: output depends on history |
| Propagation delay | The time a change takes to travel through a gate |
| Don't care (x) | An input whose value cannot affect the output |