The 4-to-1 MUX in Verilog

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The 4-to-1 MUX in one table

A reminder from Module 2. The 4-to-1 MUX reads its two select lines as a 2-bit address and routes that input to the output.

A trapezoid 4-to-1 MUX symbol with data inputs i0 to i3 stacked on the left, output y on the right

s1	s0	Address	y
0	0	0	i0
0	1	1	i1
1	0	2	i2
1	1	3	i3

The equation is just "y is the addressed input". This time you will not write it as one expression: you will build it the way Module 2 did, from three 2-to-1 MUXes.