The 2-to-4 Decoder in Verilog

The decoder in one table

A reminder from Module 2. The 2-to-4 decoder turns a 2-bit address on a and b into four one-hot outputs: exactly one is high for each address.

Each output is 1 for exactly one row, so each is its own assign.

Confirm it in the circuit

Step the address on a and b and watch the hot line move. Only ever one output is high, matching the row in the table.

AND with inverted inputs

Each output detects one input pattern by ANDing the inputs, inverting the ones that should be 0 for that code:

assign y0 = ~a & ~b;   // high only for a=0, b=0
assign y1 = ~a &  b;   // high only for a=0, b=1

Read ~a & ~b as "a is 0 and b is 0". These are the four products of a two-variable sum of products, one per output.

Build a 2-to-4 decoder

From the truth table, complete the 2-to-4 decoder in design.v. Inputs a, b; outputs y0, y1, y2, y3. The first three outputs are written for you. Add y3: the output high only on the last row, when a and b are both 1.

Use & and ~. The testbench prints the one-hot outputs for each address and passes when it prints VULKOS_RESULT: PASS.