Digital Design Fundamentals·Combinational Circuits
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Combinational logic has no memory. Its output depends only on the inputs right now, not on anything that came before. Change the inputs and the output follows.
Every circuit you built in Module 1, the gates and the multiplexer, is combinational.
The opposite kind of logic does remember. It is called sequential logic, and it is the whole of Module 3.
| Combinational | Sequential | |
|---|---|---|
| Depends on | Inputs now | Inputs now + past |
| Memory | None | Stores state |
| Example | Adder, MUX, decoder | Counter, register |
For this module, stay in the left column. Everything here reacts instantly and forgets instantly.
Figure: A single logic gate with an input waveform stepping from 0 to 1 on the left and the output waveform stepping up slightly later on the right
A gate cannot switch instantly. Charge has to move through real transistors, and that takes time. The delay between an input changing and the output settling is the propagation delay, written .
It is small, often tens of picoseconds (), but it is never zero.
When a signal passes through gates one after another, their delays add. A signal crossing three gates of each takes to come out the far end.
Chain thousands of gates and these tiny delays become the thing that limits how fast the chip can run.
Figure: A combinational circuit with inputs on the left and one output on the right, showing two routes through the gates
Signals reach the output by different routes. The critical path is simply the longest path through the gates, from any input to any output.
Its delay sets the speed of the entire circuit, because the output is not correct until the slowest signal has arrived. Nothing else about the circuit matters for speed: find the longest path, and you have found the limit.
Figure: A timing diagram of a single output wire that briefly dips to 0 and back to 1 while two input signals change at slightly different times
Because paths have different delays, signals do not all arrive at the final gate together. For a moment the output can show the wrong value before it settles.
That short wrong pulse is a glitch (or hazard). It is normal.
Glitches sound alarming, but combinational circuits are never read mid-change. The design waits for the output to settle, then uses it.
That waiting is exactly what the clock does in sequential logic: it only samples the combinational output after enough time has passed for the critical path to finish. You will see how in Module 3.
