What RTL means
You have spent two modules drawing circuits and reading truth tables. Real chips are not drawn by hand. They are described in text with a hardware description language, and a tool turns that text into gates.
The style you will write is called RTL, register transfer level. It describes what a circuit does, and synthesis works out the gates that do it. Everything you already understand, MUXes, adders, decoders, you are about to write down.
A description is not a program. It does not run top to bottom. It lays out hardware that is all active at once.
A block with a boundary
Figure: A labelled black-box diagram of a Verilog module
The unit of Verilog design is the module. It is a named block with a boundary, exactly like the blocks you drew in the hierarchy lesson.
module and_gate(
input a,
input b,
output y
);
// logic goes here
endmodule
The name is and_gate. Between the parentheses is the port list, the wires that cross the boundary. endmodule closes it.
Declaring ports
Each port has a direction:
input: a signal coming into the module from outside.output: a signal the module drives out.
module example(
input a, // comes in
input b, // comes in
output y // goes out
);
A multi-bit port carries a bus. input [7:0] data is an 8-bit input, the same [7:0] notation you met with buses in Module 1.
Two kinds of signal
Verilog has two signal types, and beginners mix them up. The rule is about how a signal gets its value, not what it stores.
wire: driven by a continuous connection, an assign or a module output. Think of a physical wire soldered to whatever drives it.reg: given its value inside a procedural always block.
For combinational logic built with assign, you use wire. In this whole module you will stay with wire. You meet reg in the sequential modules, where always blocks come in.
An output port defaults to wire, so you rarely have to write the word.
Write your first module
Write a complete module named wire_through that passes its input straight to its output.
