Introduction to Verilog

• 01Gates and operators
• 02Build an adder from gates
• 03Choosing with muxes
• 04Always blocks and case
• 05Reading simulation output
• 06Write your own testbench

What you'll learn

• Build logic gates with bitwise operators and continuous assignments
• Construct half and full adders from gates and verify them exhaustively
• Select between signals with multiplexers and the conditional operator

• 01Clocks and flip-flops
• 02Registers and resets
• 03Shift registers
• 04Counters: compute meets store

What you'll learn

• Explain why digital systems need a clock and edge-triggered storage
• Write clocked always blocks with non-blocking assignments
• Build registers with synchronous reset and enable

• 01Design brief: 8-bit ALU

What you'll learn

• Translate a written design brief into a Verilog module interface
• Implement a complete 8-bit ALU with five operations and a zero flag
• Verify the design against a full directed testbench