Complete course · 4 modules

Introduction to ASIC Design

Take your digital designs from code to real silicon. Learn the modern ASIC manufacturing flow: synthesis, technology mapping, floorplanning, static timing analysis (STA), clock trees, PPA optimization, and physical verification (DRC/LVS).

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Start with the electrical meaning of a bit. Finish by seeing how your RTL becomes silicon.

Modules: 4
Lessons: 8
Free lessons: 0
Account needed: 8

Course modules

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Module 01

Synthesis and the Gate Level

Familiarity with basic digital logic gates and Verilog syntax is recommended.

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2 lessonsLocked

Lessons

01Introduction to ASICs

What you'll learn

Contrast ASICs with FPGAs and understand standard cell libraries
Explain the role of technology mapping in RTL synthesis
Read and interpret a structural gate-level netlist

Module 02

Floorplanning and Physical Layout

Completing the Synthesis module is recommended.

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Lessons

01Floorplanning and the power grid
02Placement and routing

What you'll learn

Define core and die areas and establish physical constraints
Structure a Power Distribution Network with rings and stripes
Understand standard cell placement and metal layer routing

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Module 03

Static Timing Analysis (STA)

Understanding placement, routing, and basic flip-flop operation is required.

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Lessons

01Timing constraints: setup and hold
02Analyzing timing reports

What you'll learn

Explain setup and hold timing constraints
Calculate timing slack for launch and capture paths
Read and diagnose setup/hold violations in timing reports

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Module 04

PPA and Physical Verification

Completing the Static Timing Analysis module is recommended.

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Lessons

01Power, performance and area trade-offs
02Physical verification and tape-out

What you'll learn

Analyze Power, Performance, and Area trade-offs
Differentiate between dynamic and static leakage power
Identify physical design rule (DRC) and layout schematic (LVS) failures

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